Multiple-valued logic design based on the multiple-peak BiCMOS-NDR circuits

Design Methodology of Multiple-valued Logic Voltage-mode Storage Circuits

A novel methodology designing for Multiple-Valued Logic voltage-mode storage circuits is introduced. Using the proposed inverter-based unit, uni-signal controlled pass gates and True Single-Phase Clocked Logic-based output units, efficient r-ary (where r is the radix) dynamic and pseudo-static latches can be designed. They exhibit regular, modular, and iterative structure, which means that the ...

Design of Gates in Multiple Valued Logic

Multiple-valued logic (MVL) application in the design of digital devices opens additional opportunities. In this paper we have designed Quaternary latch & quaternary multiplexer. Multiplexer is designed with different threshold voltages. All the circuits were simulated with the Spice tool using TSMC 250 nm technology and have shown improvements in performance and power consumption and propagati...

Development of Quantum Functional Devices for Multiple-Valued Logic Circuits

Complexity Analysis of the Cost-Table Approach to the Design of Multiple-Valued Logic Circuits

We analyze the computational complexity of the cost-table approach to designing multiple-valued logic circuits that is applicable to IL, CCDs, current-mode CMOS, and RTDs. We show that this approach is NP-complete. An efficient algorithm is shown for finding the exact minimal realization of a given function by a given cost-table.

Current Mode Multiple-Valued Logic Circuits in Digital CMOS Technology

Complexity of silicon integrated circuits (IC) in very large scale of integration (VLSI) using binary logic is reaching a point where most of the silicon area is occupied with interconnecting lines among devices on the chip, which represents a drawback of the approach. First implication of the high wiring complexity is increased packing complexity with increased number of pins (in today's VLSI ...